12.3.13 Clock Monitor Control Register

Note:

Do not change the value while in operation.
CMxHWT/CMxLWT and CMxHFT/CMxLFT must all be cleared before the Fault can be injected.
When set high, the function is intended for the pulse width measurement feature where the monitored clock (as opposed to the reference clock) is expected to clock the time window generator responsible for defining the measurement time period. Conversely, the reference clock is used to clock the counter at a higher rate of switching frequency.
When set high, the content of WINPR[31:0] prescaler is ignored while both the time window generator and the counter are reset.

Name:	CMxSTAT
Offset:	0x3204, 0x3234, 0x3264, 0x3294


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					HWT	LWT	HFT	LFT
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
						TRIG	SATD	BUFV
Access						R/W	R/W	R/W
Reset						0	0	0

Bit 11 – HWT High Warning Threshold Status bit

This status bit is set by hardware when the captured count value exceeds that of the high warning threshold register content. In other words, the monitored clock is at a higher frequency than desired (or the reference clock is running slower than expected).

Value	Description
1	High threshold warning
0	No warning

Bit 10 – LWT Low Warning Threshold Status bit

This status bit is set by hardware when the captured count value is less than that of the low warning threshold register content. In other words, the monitored clock is at a lower frequency than desired (or the reference clock is running faster than expected).

Value	Description
1	Low threshold warning
0	No warning

Bit 9 – HFT High Failing Threshold Status bit

This status bit is set by hardware when the captured count value exceeds that of the high failing threshold register content. In other words, the monitored clock is at a higher frequency than allowed (or the reference clock is running slower than allowed). When instanced as a Fail-Safe Clock Monitor, a hardware switchover to the backup clock source will occur.

Value	Description
1	High threshold failing
0	No failure

Bit 8 – LFT Low Failing Threshold Status bit

This status bit is set by hardware when the captured count value is less than that of the low failing threshold register content. In other words, the monitored clock is at a lower frequency than allowed (or the reference clock is running faster than allowed). When instanced as a Fail Safe Clock Monitor, a hardware switchover to the backup clock source will occur.

Value	Description
1	Low threshold failing
0	No failure

Bit 2 – TRIG Time Window Generator Trigger Status bit

Value	Description
1	Accumulation time window has (re)started/stopped.
0	Accumulation time window has not started.

Bit 1 – SATD Counter Saturated Status bit

Counter has saturated at SAT[31:0].

Bit 0 – BUFV Buffer Valid Status bit

Value	Description
1	An accumulated count has been captured into BUF[31:0] and is ready for software use.
0	An accumulated count has not been captured into BUF[31:0] yet or has been blocked by catastrophic failure of the monitored clock for more than one accumulation window.