12.3.8 PLL Divider Register

Name:	PLLxDIV
Offset:	0x318C, 0x3198


Bit	31	30	29	28	27	26	25	24
			PLLPRE[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	1


Bit	23	22	21	20	19	18	17	16
					PLLFBDIV[11:8]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PLLFBDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	0	0	1	0	0	0


Bit	7	6	5	4	3	2	1	0
			POSTDIV1[2:0]			POSTDIV2[2:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			1	1	1	0	0	1

Bits 29:24 – PLLPRE[5:0] PLLx Reference Clock Prescale bits

The allowable PLL reference input clock frequency is 5 MHz-800 MHz.

Value	Description
111111	63x divide
111110	62x divide
...
000010	2x divide
000001	1x divide
000000	undefined, not allowed

Bits 19:16 – PLLFBDIV[11:8] PLLx Feedback Divider bits

Value	Description
111111	63x divide
111110	62x divide
...
000010	2x divide
000001	1x divide
000000	undefined, not allowed

Bits 15:8 – PLLFBDIV[7:0] PLLx Feedback Divider bits

The allowable PLL reference input clock frequency is 5 MHz-800 MHz.

Value	Description
111111	63x divide
111110	62x divide
...
000010	2x divide
000001	1x divide
000000	undefined, not allowed

Bits 5:3 – POSTDIV1[2:0] PLLx Post Divider #1 bits

Value	Description
111	7x divide
110	6x divide
...
010	2x divide
001	1x divide
000	undefined, not allowed

Bits 2:0 – POSTDIV2[2:0] PLLx Post Divider #2 bits

Value	Description
111	7x divide
110	6x divide
...
010	2x divide
001	1x divide
000	undefined, not allowed

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