12.3.15 Clock Monitor Input Selection Register

Name:	CMxSEL
Offset:	0x320C, 0x323C, 0x326C, 0x329C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	CNTSEL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	7	6	5	4	3	2	1	0
	WINSEL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset

Bits 15:8 – CNTSEL[7:0] Counter Clock Source bits

Selects the monitored clock source. See Table 12-5.

Bits 7:0 – WINSEL[7:0] Window Clock Source bits

Selects reference clock source. See Table 12-5.

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