12.3.1 System Clock Control Register
Legend: HS = Hardware Settable bit, HC = Hardware Clearable bit
| Name: | OSCCTRL |
| Offset: | 0x3100 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DIAGLOCK | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CLKLOCK | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PLL2RDY | PLL1RDY | LPRCRDY | AOSCRDY | SOSCRDY | POSCRDY | BFRCRDY | FRCRDY | ||
| Access | HS/HC/R | HS/HC/R | HS/HC/R | HS/HC/R | HS/HC/R | HS/HC/R | HS/HC/R | HS/HC/R | |
| Reset | 0 | 0 | x | x | x | 0 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PLL2EN | PLL1EN | LPRCEN | AOSCEN | SOSCEN | POSCEN | BFRCEN | FRCEN | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – DIAGLOCK Clock Diagnostic Lock Enable bit
| Value | Description |
|---|---|
| 1 | Clock diagnostic register (CLK_DIAG) is locked. |
| 0 | Clock diagnostic register is not locked; configurations may be modified, |
Bit 23 – CLKLOCK Clock Lock Enable bit
| Value | Description |
|---|---|
| 1 | Clock registers are locked. |
| 0 | Clock registers are not locked;configurations may be modified. |
Bit 15 – PLL2RDY PLL2 Ready Status bit
| Value | Description |
|---|---|
| 1 | PLL2 Ready |
| 0 | PLL2 Not ready |
Bit 14 – PLL1RDY PLL1 Ready Status bit
| Value | Description |
|---|---|
| 1 | PLL1 Ready |
| 0 | PLL1 Not ready |
Bit 13 – LPRCRDY LPRC Ready Status bit
| Value | Description |
|---|---|
| 1 | Low-power 32 KHz RC oscillator ready |
| 0 | Low-power 32 KHz RC oscillator not ready |
Bit 12 – AOSCRDY Auxiliary Crystal Oscillator Ready Status bit
| Value | Description |
|---|---|
| 1 | Auxiliary crystal oscillator ready |
| 0 | Auxiliary crystal oscillator not ready |
Bit 11 – SOSCRDY Secondary Crystal Oscillator Ready Status bit
| Value | Description |
|---|---|
| 1 | Secondary crystal oscillator ready |
| 0 | Secondary crystal oscillator not ready |
Bit 10 – POSCRDY Primary Crystal Oscillator Ready Status bit
| Value | Description |
|---|---|
| 1 | Primary crystal/resonator oscillator ready |
| 0 | Primary crystal/resonator oscillator not ready |
Bit 9 – BFRCRDY Backup FRC Ready Status bit
| Value | Description |
|---|---|
| 1 | Backup FRC oscillator ready |
| 0 | Backup FRC oscillator not ready |
Bit 8 – FRCRDY 8 MHz FRC Ready Status bit
| Value | Description |
|---|---|
| 1 | FRC oscillator ready |
| 0 | FRC oscillator not ready |
Bit 7 – PLL2EN PLL2 Enable bit
| Value | Description |
|---|---|
| 1 | Enable PLL2. |
| 0 | Disable PLL2. |
Bit 6 – PLL1EN PLL1 Enable bit
| Value | Description |
|---|---|
| 1 | Enable PLL1. |
| 0 | Disable PLL1. |
Bit 5 – LPRCEN LPRC Clock Enable bit
| Value | Description |
|---|---|
| 1 | Enable low-power 32 KHz RC oscillator. |
| 0 | Disable low-power 32 KHz RC oscillator. |
Bit 4 – AOSCEN Auxiliary Crystal Clock Enable bit
| Value | Description |
|---|---|
| 1 | Enable auxiliary crystal oscillator. |
| 0 | Disable auxiliary crystal oscillator. |
Bit 3 – SOSCEN Secondary Crystal Clock Enable bit
| Value | Description |
|---|---|
| 1 | Enable secondary crystal oscillator. |
| 0 | Disable secondary crystal oscillator. |
Bit 2 – POSCEN Primary Crystal Clock Enable bit
| Value | Description |
|---|---|
| 1 | Enable primary crystal/resonator oscillator. |
| 0 | Disable primary crystal/resonator oscillator. |
Bit 1 – BFRCEN Backup FRC Clock Enable bit
| Value | Description |
|---|---|
| 1 | Enable backup FRC oscillator. |
| 0 | Disable backup FRC oscillator. |
Bit 0 – FRCEN 8 MHz FRC Clock Enable bit
| Value | Description |
|---|---|
| 1 | Enable FRC oscillator. |
| 0 | Disable FRC oscillator. |