12.3.17 Clock Monitor Saturation Register
| Name: | CMxSAT |
| Offset: | 0x3214, 0x3244, 0x3274, 0x32A4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SAT[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SAT[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SAT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
Bits 31:0 – SAT[31:0] Clock Monitor Counter Saturation bits
The Clock Monitor Counter Saturation register contains the accumulated count value which causes the counter to saturate. If the counter has reached the count value programmed into this register before being captured, the CMxSATD bit is set with an interrupt invoked.