15.4.3.2.5 Center-Aligned PWM Mode

Center-Aligned PWM mode signals avoid coincident rising or falling edges between PWM Generators when the duty cycles are different, reducing excessive current ripple and filtering requirements in power inverter applications.

The PWM pulse maintains symmetry around the end of the first timer cycle and the beginning of the second cycle. If the duty cycle of the PWM signal is increased, then the position of the rising edge and the falling edge will change to maintain this symmetry. Center-Aligned PWM mode is selected when MODSEL[2:0] (PGxCON[2:0]) = 100. Center-Aligned PWM Operating mode uses two timer cycles to produce a single pulse. The characteristics of the PWM signal are defined by two SFRs:

• PGxDC: Determines the width of the PWM pulse from the center of the two timer cycles.
• PGxPER: Determines the end of the PWM timer count cycle.

The falling edge occurs when the PWM Generator Timer = PGxDC and the rising edge occurs when the PG Timer = PGxPER – PGxDC + 1. An offset of 1 is added to the rising edge calculation to produce symmetry between the two timer count cycles. A PGxDC value of ‘1’, for example, will produce a pulse that is two cycles in duration. When PGxDC = 0, there are restrictions on the maximum PER value. In standard resolution, the max value is 0xFFFE. If the PER value is above this value, a short pulse at EOC may occur.

The timer cycle is tracked using the CAHALF status bit (PGxSTAT[1]) and is read as ‘0’ on the first half of cycle and ‘1’ on the second half. Buffer updates to the duty cycle or period are allowed only at the beginning of the first timer cycle. The End-of-Cycle (EOC) interrupt is generated only after the completion of both period cycles. Figure 15-10 shows the relationship between the control SFRs and the output waveform. See Data Buffering for additional information on data buffering.

Center-Aligned mode data restrictions and behavior: