15.4.3.2.2 Variable Phase PWM Mode

The Variable Phase PWM mode differs from Independent Edge mode in that one register is used to select the phase offset from the Start-of-Cycle, and a second register is used to select the width of the pulse. The Variable Phase PWM mode is useful as the PGxDC register is programmed to a constant value, while the PGxPHASE value is modulated. The PWM logic will automatically calculate rising edge and falling edge times to maintain a constant pulse width. Similarly, the user can leave the PGxPHASE register programmed to a constant value to create signals with a constant phase offset and variable duty cycle. The Variable Phase PWM mode is selected when MODSEL[2:0] (PGxCON[2:0]) = 001. The characteristics of the PWM signal are determined by these three SFRs:

  • PGxPHASE: Determines the offset of the PWM signal rising edge from the start of the 
timer cycle.
  • PGxDC: Determines the width of the PWM pulse and location of the PWM signal 
falling edge.
  • PGxPER: Determines the end of the PWM timer count cycle.

When updating PER in Variable Phase mode, ensure that the client PWM Generator PER > host PER. The recommended method is client PER = host PER + max PHASE to ensure that the client PWM Generator does not generate its own SOC.

The host will always provide an SOC to trigger the client PWM Generators. If the host PER is lengthened such that client PER > host PER, a client PWM cycle may be missed as the host SOC trigger arrives when the client cycle is in progress and the trigger is ignored.

Figure 15-6 shows the relationship between the control SFRs and the output waveform.

Figure 15-6. Variable Phase PWM Mode

The Master Duty Cycle SFR (MDC) can also be used to change the duty cycle of all phases with a single register write. An example of a multiphase system is shown in Figure 15-7. Variable Phase mode cannot support active duty cycles across EOC boundaries. Ensure Phase + DC ≤ Period to allow for completion of the duty cycle for EOC.

In this scenario, PG1 provides SOC triggers to PG2-PG4. The output wave form is shown in Figure 15-7.

  1. Set all PGs to same clock source.
  2. Set all PGs in Variable Phase mode, MODSEL = 0b001.
  3. Set PG1 for self trigger, SOCS = 0b0000.
  4. Set PG2-PG4 to use PG1's SOC trigger, SOCS = 0b0001.
  5. Write initial PER, DC and PHASE to all PGs.
  6. Enable outputs, PENx = '1'.
  7. Set ON = '1' of PG2-PG4. No cycles will start until PG1 sends trigger.
  8. Set ON = '1' of PG1. This will start all PG synchronously.
Figure 15-7. Multiphase PWM Example