The Store Program Memory Control and Status Register contains the control bits needed
to control the Boot Loader operations.
When addressing I/O registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be
supported within the 64 locations reserved in Opcode for the IN and OUT
instructions. For the extended I/O space from 0x60 in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
SPM Interrupt
Enable
When the SPMIE bit
is written to one, and the I-bit in the Status Register is set (one), the SPM ready
interrupt will be enabled. The SPM ready Interrupt will be executed as long as the
SPMEN bit in the SPMCSR Register is cleared.
Read-While-Write
Section Busy
When a
Self-Programming (Page Erase or Page Write) operation to the RWW section is
initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the
RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is
written to one after a Self-Programming operation is completed. Alternatively, the
RWWSB bit will automatically be cleared if a page load operation is
initiated.
Signature Row
Read
If this bit is
written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register.
Refer to Reading the Fuse and Lock Bits from Software in this chapter. An SPM
instruction within four cycles after SIGRD and SPMEN are set will have no effect.
This operation is reserved for future use and should not be
used.
Read-While-Write
Section Read Enable
When programming
(Page Erase or Page Write) to the RWW section, the RWW section is blocked for
reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user
software must wait until the programming is completed (SPMEN will be cleared). Then,
if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM
instruction within four clock cycles re-enables the RWW section. The RWW section
cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write
(SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the
Flash load operation will abort and the data loaded will be
lost.
Boot Lock Bit
Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction
within four clock cycles sets Boot Lock bits and Memory Lock bits, according to
the data in R0. The data in R1 and the address in the Z-pointer are ignored. The
BLBSET bit will automatically be cleared upon completion of the Lock bit set, or
if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are
set in the SPMCSR Register (SPMCSR.BLBSET and SPMCSR.SPMEN), will read either
the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. Refer to Reading the Fuse and Lock Bits from
Software in this chapter.
Page Write
If this bit is
written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are
ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM
instruction is executed within four clock cycles. The CPU is halted during the
entire Page Write operation if the NRWW section is addressed.
Page Erase
If this bit is written to one at the same time as SPMEN, the next
SPM instruction within four clock cycles executes Page Erase. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction
is executed within four clock cycles. The CPU is halted during the entire Page Write
operation if the NRWW section is addressed.
Store Program Memory
This bit enables the
SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a
special meaning (see the description above). If only SPMEN is written, the following
SPM instruction will store the value in R1:R0 in the temporary page buffer addressed
by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear
upon completion of an SPM instruction, or if no SPM instruction is executed within
four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high
until the operation is completed.
Writing any other combination than
“0x10001”, “0x01001”, “0x00101”, “0x00011” or “0x00001” in the lower five bits
will have no effect.