Table 1. SPI Timing Parameters
|
Description |
Mode |
Min. |
Typ |
Max |
Units |
1 |
SCK
period |
Master |
- |
See Table 3 |
- |
ns |
2 |
SCK
high/low |
Master |
- |
50% duty
cycle |
- |
3 |
Rise/Fall
time |
Master |
- |
3.6 |
- |
4 |
Setup |
Master |
- |
10 |
- |
5 |
Hold |
Master |
- |
10 |
- |
6 |
Out to
SCK |
Master |
- |
0.5 •
tsck |
- |
7 |
SCK to
out |
Master |
- |
10 |
- |
8 |
SCK to out
high |
Master |
- |
10 |
- |
9 |
SS low to out |
Slave |
- |
15 |
- |
10 |
SCK
period |
Slave |
4 •
tck |
- |
- |
11 |
SCK
high/low(1) |
Slave |
2 •
tck |
- |
- |
12 |
Rise/Fall
time |
Slave |
- |
- |
1600 |
13 |
Setup |
Slave |
10 |
- |
- |
14 |
Hold |
Slave |
tck |
- |
- |
15 |
SCK to
out |
Slave |
- |
15 |
- |
16 |
SCK to
SS high |
Slave |
20 |
- |
- |
17 |
SS high to tri-state |
Slave |
- |
10 |
- |
18 |
SS low to SCK |
Slave |
2 •
tck |
- |
- |
Notes:
- 1.In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK > 12 MHz
Figure 1. SPI Interface Timing Requirements
(Master Mode)
Figure 2. SPI Interface Timing Requirements
(Slave Mode)