TC3 Control Register B


Bit 7 – ICNC3: Input Capture Noise Canceler

Input Capture Noise Canceler

Writing this bit to '1' activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP3) is filtered. The filter function requires four successive equal valued samples of the ICP3 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.

Bit 6 – ICES3: Input Capture Edge Select

Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICP3) that is used to trigger a capture event. When the ICES3 bit is written to zero, a falling (negative) edge is used as a trigger, and when the ICES3 bit is written to '1', a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICES3 setting, the counter value is copied into the Input Capture Register (ICR3). The event will also set the Input Capture Flag (ICF3), and this can be used to cause an Input Capture Interrupt if this interrupt is enabled.

When the ICR3 is used as TOP value (see description of the WGM13:0 bits located in the TCCR3A and the TCCR3B Register), the ICP3 is disconnected and consequently, the Input Capture function is disabled.

Bits 2:0 – CS3[2:0]: Clock Select 3

Clock Select 3

The three Clock Select bits select the clock source to be used by the Timer/Counter. Refer to Figure 1 and Figure 2.

Table 1. Clock Select Bit Description
CS32 CS31 CS30 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clkI/O/1 (No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clkI/O/1024 (From prescaler)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.

Bits 3, 4 – WGM3: Waveform Generation Mode

Waveform Generation Mode

Refer to TCCR1A.