8-bit AVR Microcontrollers

Timer/Counter 3 Interrupt Mask Register

Name:
TIMSK3
Offset:
0x71
Reset:
0x00
Access:
-
Bit76543210
ICIE3OCIE3BOCIE3ATOIE3
AccessR/WR/WR/WR/W
Reset0000

Bit 5 – ICIE3: Timer/Counter 3, Input Capture Interrupt Enable

Timer/Counter 3, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF3 Flag, located in TIFR3, is set.

Bit 2 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable

Timer/Counter3, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter 3 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF3B Flag, located in TIFR3, is set.

Bit 1 – OCIE3A: Timer/Counter 3, Output Compare A Match Interrupt Enable

Timer/Counter 3, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter 3 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF3A Flag, located in TIFR3, is set.

Bit 0 – TOIE3: Timer/Counter 3, Overflow Interrupt Enable

Timer/Counter 3, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter 3 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV3 Flag, located in TIFR3, is set.