Timer/Counter 3, Input
Capture Interrupt Enable
When this bit is written to one,
and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt
Vector is executed when the ICF3 Flag, located in TIFR3, is set.
Timer/Counter3,
Output Compare B Match Interrupt Enable
When this bit is
written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter 3 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector is executed when the OCF3B Flag, located in TIFR3, is
set.
Timer/Counter 3,
Output Compare A Match Interrupt Enable
When this bit is
written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter 3 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector is executed when the OCF3A Flag, located in TIFR3, is
set.
Timer/Counter 3,
Overflow Interrupt Enable
When this bit is
written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter 3 Overflow interrupt is enabled. The corresponding
Interrupt Vector is executed when the TOV3 Flag, located in TIFR3, is
set.