USART I/O Data Register n

The USART Transmit Data Buffer (TXB) register and USART receive data buffer registers share the same I/O address referred to as USART data register or UDRn. The TXB will be the destination for data written to the UDR1 register location. Reading the UDRn register location will return the contents of the Receive Data Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver.

The transmit buffer can only be written when the UDRE flag in the UCSRnA register is set. Data is written to UDRn when the UCSRnA.UDRE flag is not set, will be ignored by the USART Transmitter n. When data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the transmit shift register when the shift register is empty. Then the data will be serially transmitted on the TxDn pin.

The receive buffer consists of a two-level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO.

0xC6 + n*0x01 [n=0..1]
TXB / RXB[7:0]

Bits 7:0 – TXB / RXB[7:0]: USART Transmit / Receive Data Buffer

USART Transmit / Receive Data Buffer