In Transmit mode, TWDRn contains the next byte to be transmitted. In Receive mode, the TWDRn contains the last byte received. It is writable while the TWI n is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag in the TWI Control Register n (TWCRn.TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDRn remains stable as long as TWCRn.TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDRn always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI n interrupt. In this case, the contents of TWDRn is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.