Timer/Counter 1,
Input Capture Interrupt Enable
When this bit is
written to '1', and the I-flag in the Status register is set (interrupts globally
enabled), the Timer/Counter 1 Input Capture interrupt is enabled. The corresponding
Interrupt Vector is executed when the ICF1 flag, located in TIFR1, is
set.
Timer/Counter 1,
Output Compare B Match Interrupt Enable
When this bit is
written to '1', and the I-flag in the Status register is set (interrupts globally
enabled), the Timer/Counter 1 Output Compare B Match interrupt is enabled. The
corresponding interrupt vector is executed when the OCF1B flag, located in TIFR1, is
set.
Timer/Counter 1,
Output Compare A Match Interrupt Enable
When this bit is
written to '1', and the I-flag in the Status register is set (interrupts globally
enabled), the Timer/Counter 1 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector is executed when the OCF1A Flag, located in TIFR1, is
set.
Timer/Counter 1,
Overflow Interrupt Enable
When this bit is
written to '1', and the I-flag in the Status register is set (interrupts globally
enabled), the Timer/Counter 1 Overflow interrupt is enabled. The corresponding
interrupt vector is executed when the TOV flag, located in TIFR1, is
set.