8-bit AVR Microcontrollers

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the Asynchronous and the Synchronous Master modes of operation. The description in this section refers to the clock generation logic block diagram in the previous section.

The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnL register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRRn+1)). The transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on the mode. The baud rate generator output is used directly by the receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8, or 16 states depending on the mode set by the state of the UMSEL, U2Xn and DDR_XCK bits.

The table below contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source.

Table 1. Equations for Calculating Baud Rate Register Setting
Operating Mode Equation for Calculating Baud Rate(1) Equation for Calculating UBRRn Value
Asynchronous Normal mode (U2Xn = 0)
Asynchronous Double Speed mode (U2Xn = 1)
Synchronous Master mode
Note: 1. The baud rate is defined to be the transfer rate in bits per second (bps)
Baud rate (in bits per second, bps)
System oscillator clock frequency
Contents of the UBRRnH and UBRRnL registers, (0-4095).

Some examples of UBRRn values for some system clock frequencies are found in Examples of Baud Rate Settings.