43.7.70 ISC DMA Configuration Register

Name: ISC_DCFG
Offset: 0x51C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 AWQOS[3:0]ARQOS[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
      CMBSIZE[2:0] 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
  YMBSIZE[2:0] IMODE[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 23:20 – AWQOS[3:0] Write QoS Value

If AWQOS is set to 0, the QoS value depends on the output FIFO level (dynamic configuration). Otherwise the value is defined in the register.

Bits 19:16 – ARQOS[3:0] Read QoS Value

Returns the QoS bus value when a descriptor is retrieved from the memory.

Bits 10:8 – CMBSIZE[2:0] DMA Memory Burst Size C channel

ValueNameDescription
0 SINGLE

DMA single access

1 BEATS4

4-beat burst access

2 BEATS8

8-beat burst access

3 BEATS16

16-beat burst access

4 BEATS32 32-beat burst access

Bits 6:4 – YMBSIZE[2:0] DMA Memory Burst Size Y channel

ValueNameDescription
0 SINGLE

DMA single access

1 BEATS4

4-beat burst access

2 BEATS8

8-beat burst access

3 BEATS16

16-beat burst access

4 BEATS32 32-beat burst access

Bits 2:0 – IMODE[2:0] DMA Input Mode Selection

ValueNameDescription
0 PACKED8

8 bits, single channel packed

1 PACKED16

16 bits, single channel packed

2 PACKED32

32 bits, single channel packed

3 YC422SP

32 bits, dual channel

4 YC422P

32 bits, triple channel

5 YC420SP

32 bits, dual channel

6 YC420P

32 bits, triple channel