The following
configuration values are valid for all listed bit names of this register:
0: The
corresponding source of interrupt is disabled.
1: The corresponding source of
interrupt is enabled.
Name:
ISC_INTMASK
Offset:
0x30
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
WPE
GFOV
CCIRERR
HDTO
VDTO
DAOV
VFPOV
Access
W
W
R
R
R
R
R
Reset
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RERR
WERR
Access
R
R
Reset
0
0
Bit
15
14
13
12
11
10
9
8
HISCLR
HISDONE
LDONE
DDONE
Access
R
R
R
R
Reset
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DIS
SWRST
HD
VD
Access
R
R
R
R
Reset
0
0
0
0
Bit 30 – WPE Write Protection Error Interrupt Mask
Bit 29 – GFOV FIFO Overflow
Interrupt Mask
Bit 28 – CCIRERR CCIR Decoder Error Interrupt Mask
Bit 27 – HDTO Horizontal Synchronization Timeout Interrupt Mask
Bit 26 – VDTO Vertical Synchronization Timeout Interrupt Mask
Bit 25 – DAOV Data Overflow Interrupt Mask
Bit 24 – VFPOV Vertical Front Porch Overflow Interrupt Mask
Bit 20 – RERR Read Channel Error Interrupt Mask
Bit 16 – WERR Write Channel Error Interrupt Mask
Bit 13 – HISCLR Histogram Clear Interrupt Mask
Bit 12 – HISDONE Histogram Completed Interrupt Mask
Bit 9 – LDONE DMA List Done Interrupt Mask
Bit 8 – DDONE DMA Done Interrupt Mask
Bit 5 – DIS Disable Completed Interrupt Mask
Bit 4 – SWRST Software Reset Completed Interrupt Mask
Bit 1 – HD Horizontal Synchronization Detection Interrupt Mask
Bit 0 – VD Vertical Synchronization Detection Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
