43.7.46 ISC HXS Configuration Register

This register can only be written if WPCFGEN is cleared in ISC_WPMR.

Name:	ISC_HXS_CFG
Offset:	0x3B0
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
					FL[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					OFFSET[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
				TAP2			FILTCFG[1:0]
Access				R/W			R/W	R/W
Reset				0			0	0

Bits 27:24 – FL[3:0] Flush Latency

Defines the minimum number of valid cycles between two lines.

Bits 11:8 – OFFSET[3:0] Resampling Default Phase

Defines the phase initialization of the filter.

Bit 4 – TAP2 Bilinear Interpolation

Value	Description
0	Custom tap values are used (see ISC_HXS_TAP10PHI).
1	Bilinear interpolation is used.

Bits 1:0 – FILTCFG[1:0] Horizontal Filter Initial Configuration

Defines how the resampling filter will be initialized. Use value 1 for RGB interpolated pixel stream.

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