43.7.17 ISC Defective Pixel Correction Median Threshold Register
This register can only be written if WPCFGEN is cleared in
ISC_WPMR.
Name:
ISC_DPC_THRESHM
Offset:
0x48
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
THRESHM[11:8]
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
7
6
5
4
3
2
1
0
THRESHM[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 11:0 – THRESHM[11:0] Median Threshold
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