43.7.4 ISC Parallel Front End Configuration 0 Register

This register can only be written if WPCFGEN is cleared in ISC_WPMR.

Name:	ISC_PFE_CFG0
Offset:	0x0C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	REP	BPS[2:0]			CCIR_REP
Access	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SKIPCNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
		MIPI	ROWEN	COLEN	CCIR10_8N	CCIR_CRC	CCIR656	GATED
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CONT	MODE[2:0]			FPOL	PPOL	VPOL	HPOL
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – REP Up Multiply with Replication

Value	Description
0	Unused bits are stuck at 0.
1	Unused bits are copied from MSB.

Bits 30:28 – BPS[2:0] Bits Per Sample

Value	Name	Description
0	TWELVE	12-bit input
1	ELEVEN	11-bit input
2	TEN	10-bit input
3	NINE	9-bit input
4	EIGHT	8-bit input
5	FORTY	40-bit input (used for MIPI formats up to forty bits per pixel)

Bit 27 – CCIR_REP CCIR Replication

Value	Description
0	Unused bits are stuck at 0.
1	Unused bits are copied from MSB.

Bits 23:16 – SKIPCNT[7:0] Frame Skipping Counter

Bit 14 – MIPI MIPI Interface Connection

Value	Description
0	Input data come from the physical parallel interface.
1	Input data come from the physical MIPI interface.

Bit 13 – ROWEN Row Cropping Enable

Value	Description
0	Row Cropping is disabled.
1	Row Cropping is enabled.

Bit 12 – COLEN Column Cropping Enable

Value	Description
0	Column Cropping is disabled.
1	Column Cropping is enabled.

Bit 11 – CCIR10_8N CCIR 10 bits or 8 bits

Value	Description
0	8-bit mode.
1	10-bit mode.

Bit 10 – CCIR_CRC CCIR656 CRC Decoder

Value	Description
0	Embedded CRC is discarded.
1	Embedded CRC is decoded.

Bit 9 – CCIR656 CCIR656 input mode

Value	Description
0	HSYNC and VSYNC signals are used to synchronize the input stream.
1	Embedded synchronization is used.

Bit 8 – GATED Gated input clock

Value	Description
0	The external pixel clock is free running.
1	The external pixel clock is gated.

Bit 7 – CONT Continuous Acquisition

Value	Description
0	Single Shot mode.
1	Video mode.

Bits 6:4 – MODE[2:0] Parallel Front End Mode

Value	Name	Description
0	PROGRESSIVE	Video source is progressive.
1	DF_TOP	Video source is interlaced, two fields are captured starting with top field.
2	DF_BOTTOM	Video source is interlaced, two fields are captured starting with bottom field.
3	DF_IMMEDIATE	Video source is interlaced, two fields are captured immediately.
4	SF_TOP	Video source is interlaced, one field is captured starting with the top field.
5	SF_BOTTOM	Video source is interlaced, one field is captured starting with the bottom field.
6	SF_IMMEDIATE	Video source is interlaced, one field is captured starting immediately.

Bit 3 – FPOL Field Polarity

Value	Description
0	Top field is sampled when F value is 0; Bottom field is sampled when F value is 1.
1	Top field is sampled when F value is 1; Bottom field is sampled when F value is 0.

Bit 2 – PPOL Pixel Clock Polarity

Value	Description
0	The pixel stream is sampled on the rising edge of the pixel clock.
1	The pixel stream is sampled on the falling edge of the pixel clock.

Bit 1 – VPOL Vertical Synchronization Polarity

Value	Description
0	VSYNC signal is active high, i.e. valid pixels are sampled when VSYNC is asserted.
1	VSYNC signal is active low, i.e. valid pixels are sampled when VSYNC is deasserted.

Bit 0 – HPOL Horizontal Synchronization Polarity

Value	Description
0	HSYNC signal is active high, i.e. valid pixels are sampled when HSYNC is asserted.
1	HSYNC signal is active low, i.e. valid pixels are sampled when HSYNC is deasserted.

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