43.7.11 ISC Interrupt Enable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the interrupt.

This register can only be written if WPITEN is cleared in ISC_WPMR.

Name:	ISC_INTEN
Offset:	0x28
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24
		WPE	GFOV	CCIRERR	HDTO	VDTO	DAOV	VFPOV
Access		W	W	W	W	W	W	W
Reset		–	–	–	–	–	–	–


Bit	23	22	21	20	19	18	17	16
				RERR				WERR
Access				W				W
Reset				–				–


Bit	15	14	13	12	11	10	9	8
			HISCLR	HISDONE			LDONE	DDONE
Access			W	W			W	W
Reset			–	–			–	–


Bit	7	6	5	4	3	2	1	0
			DIS	SWRST			HD	VD
Access			W	W			W	W
Reset			–	–			–	–

Bit 30 – WPE Write Protection Error Enable

Bit 29 – GFOV Input FIFO Overflow Interrupt Enable

Bit 28 – CCIRERR CCIR Decoder Error Interrupt Enable

Bit 27 – HDTO Horizontal Synchronization Timeout Interrupt Enable

Bit 26 – VDTO Vertical Synchronization Timeout Interrupt Enable

Bit 25 – DAOV Data Overflow Interrupt Enable

Bit 24 – VFPOV Vertical Front Porch Overflow Interrupt Enable

Bit 20 – RERR Read Channel Error Interrupt Enable

Bit 16 – WERR Write Channel Error Interrupt Enable

Bit 13 – HISCLR Histogram Clear Interrupt Enable

Bit 12 – HISDONE Histogram Completed Interrupt Enable

Bit 9 – LDONE DMA List Done Interrupt Enable

Bit 8 – DDONE DMA Done Interrupt Enable

Bit 5 – DIS Disable Completed Interrupt Enable

Bit 4 – SWRST Software Reset Completed Interrupt Enable

Bit 1 – HD Horizontal Synchronization Detection Interrupt Enable

Bit 0 – VD Vertical Synchronization Detection Interrupt Enable

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