43.7.9 ISC Clock Status Register
| Name: | ISC_CLKSR |
| Offset: | 0x20 |
| Reset: | 0x00000001 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SIP | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MCSR | ICSR | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 1 |
Bit 31 – SIP Synchronization In Progress
| Value | Description |
|---|---|
| 0 | The double domain synchronization operation is over. |
| 1 | The double domain synchronization operation is in progress. |
Bit 1 – MCSR Camera Sensor Clock Status Register
| Value | Description |
|---|---|
| 0 | The camera sensor clock is disabled. |
| 1 | The camera sensor clock is enabled. |
Bit 0 – ICSR ISP Clock Status Register
| Value | Description |
|---|---|
| 0 | The ISP clock is disabled. |
| 1 | The ISP clock is enabled. |