43.7.45 ISC VXS Configuration Register
This register can only be written if WPCFGEN is cleared in ISC_WPMR.
| Name: | ISC_VXS_CFG |
| Offset: | 0x3AC |
| Reset: | 0x80000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FLMAX[3:0] | FLMIN[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OFFSET[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TAP2 | FILTCFG[1:0] | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 31:28 – FLMAX[3:0] Flush Latency Maximum
Bits 27:24 – FLMIN[3:0] Flush Latency Minimum
Bits 11:8 – OFFSET[3:0] Resampling Default Phase
Bit 4 – TAP2 Bilinear Interpolation
| Value | Description |
|---|---|
| 0 |
Custom tap values are used (see ISC_VXS_TAP10PHI). |
| 1 |
Bilinear interpolation is used. |