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43.7.23 ISC White Balance Offset for R, GR Register
This register can only be written if WPCFGEN is cleared in
ISC_WPMR .
Name: ISC_WB_O_RGR Offset: 0x60 Reset: 0x00000000 Property: Read/Write
Bit 31 30 29 28 27 26 25 24 GROFST[12:8] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 GROFST[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 ROFST[12:8] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 ROFST[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 28:16 – GROFST[12:0] Offset Green Component for Red Row (signed 13 bits
1:12:0)
Bits 12:0 – ROFST[12:0] Offset Red Component (signed 13 bits
1:12:0)
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