43.2 Power Supply

Table 43-5. Power Supply Electrical Specifications
DC CHARACTERISTICS			Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typical	Max.	Units	Conditions
REG_1	VDDCORE_CIN	VDDCORE Input Bypass parallel Capacitor pair	0.8	1	1.2	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω (Immediately adjacent to pin)
REG_3	VDDCORE_CIN	VDDCORE Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to pin)
REG_4	VDDIO_CIN	VDDIO Input Bypass parallel Capacitor pair	8	10⁽⁵⁾	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω ^(1,6)
REG_5	VDDIO_CIN	VDDIO Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to all VDDIO pins)⁽⁶⁾
REG_7	VDDIN_CIN	VDDIN Input Bypass parallel Capacitor pair	8	10⁽⁶⁾	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω ⁽¹⁾
REG_8	VDDIN_CIN	VDDIN Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to all VDDIN pins)
REG_9	VREFx_CIN	External VREFx Input Bypass parallel Capacitor pair ⁽⁷⁾	3.76	4.7	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω⁽⁶⁾
REG_11	VREFx_CIN	External VREFx Input Bypass parallel Capacitor pair ⁽⁷⁾	80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to pin)⁽⁶⁾
REG_17	VDDANA_CIN	VDDANA Input Bypass parallel Capacitor pair	8	10	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω ^(1,6)(as close as possible to pin)
REG_19	VDDANA_CIN	VDDANA Input Bypass parallel Capacitor pair	80	100	—	nf	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to pin)⁽⁶⁾
REG_23	VDDANA_LEXT	VDDANA series Ferrite Bead DCR (DC Resistance)	—	—	0.1	Ω	≥600 Ohms @ 100 MHz
REG_25	VDDANA_LEXT	Ferrite Bead current rating	500	—	—	mA
REG_37	VDDIO, VDDIN, VDDANA ⁽²⁾	VDDIO, VDDIN, VDDANA Input Voltage Range	2.7	—	5.5	V	—
REG_38	IVDD_{IO_MAX}	VDDIO max current	—	—	92	mA	I/O pin configured as inputs
REG_39	VDDCORE	DC calibrated output voltage	1.08	1.23	1.32	V	—
REG_41A	IVDD_{CORE_MAX}	VDDCORE max current	—	—	2.3	mA	LDO mode
REG_41B	IVDD_{CORE_MAX}	VDDCORE max current	—	—	302	µa	Standby mode
REG_43	SVDDIO/VDD_R	VDDIN, VDDANA, VDDIO Rise Ramp Rate to Ensure Internal Power-on Reset Signal	—	—	0.1	V/µs	Failure to meet this specification may lead to start-up or unexpected behaviors
REG_44	SVDDIO/VDD_F	VDDIO Falling Ramp Rate to Ensure Internal Power-on Reset Signal	—	—	0.05	V/µs	Failure to meet this specification may cause the device to not detect reset
REG_45A	VPOR+	VDDIO/VDD Rising Power-on Reset	2.49	—	2.58	V	VDDIO Power- up power -down (See Param REG_43, VDDIO/VDD Ramp Rate)
REG_45B	VPOR-	VDDIO/VDD Falling Power-on Reset	1.64	—	1.92	V	VDDIO Power- up or Power-down (See Param REG_43, VDDIO/VDD Ramp Rate)
REG_47	VBODVDD	VDDIO BOD (All modes)	2.74	2.80	2.86	V	(Default Setting) LEVEL[5:0] = 0x8 ⁽³⁾ HYST[0] = 0x0
			2.74	2.86	2.91	V	(Default Setting) LEVEL[5:0] = 0x8 ^(3,4) HYST[0] = 0x1
			5.27	5.41	5.48	V	LEVEL[5:0] = 0x3F (3) HYST[0] = 0x0
			5.27	5.50	5.57	V	LEVEL[5:0] = 0x3F ^(3,4)HYST[0] = 0x1
REG_51	VBODVDDLEVEL_STEP	VBODVDD step size, LEVEL[5:0]	—	47	—	mV	—
REG_52	VBODVDDHYST_STEP	VBODVDD Hysterisis	—	See note ⁽⁴⁾	—	—	—
REG_53	TRST	External RESET valid active pulse width	1.1	—	—	µs	Minimum reset active time to guarantee CPU reset
Note: In single power supply configuration, only one bulk capacitor (REG_4 or REG_7) is enough for both VDDIN and VDDIO. In dual-power supply configuration, two bulk capacitors are needed: REG_4 for VDDIO and REG_7 for VDDIN. VDDIN and VDDANA must be at the same voltage level. VDDIO should be lower or equal to VDDIN/ VDDANA. The common voltage is referred to as VDD in the data sheet. Some I/O are in the VDDIO cluster, but can be multiplexed as analog inputs or outputs (e.g. TCC[n] pads). In such a case, VDDANA is used to power the I/O. Using this configuration may result in an electrical conflict if the VDDIO voltage is lower than the VDDIN/VDDANA. VBODVDD-(min) = 2.372 + (BODVDD.LEVEL[5:0]) * 0.047 VBODVDD_{HYST_STEP} Graph: VBODVDD(max)@BODVDD.HYST[0] =1 = VBODVDD(max)@BODVDD.HYST[0] = 0 + VBODVDDHYST_STEP Shared between VDDIO, VDDIN, and VDDANA in case of a common power supply VDD = VDDIO = VDDIN = VDDANA. Shared between VDDIO, VDDIN, and VDDANA in case of a common power supply VDD = VDDIO = VDDIN = VDDANA. Else, shared between VDDIN = VDDANA. If the VREF is not used, then the caps are not needed.