43.29 Position Decoder (PDEC) Electrical Specifications
AC CHARACTERISTICS | Standard
Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial |
||||||
---|---|---|---|---|---|---|---|
Param. No. | Symbol | Characteristics | Min. | Typ | Max. | Units | Conditions |
PDEC_1 | TtPH | TPCK high time | 2/fGCLK_PDEC | — | — | ns | VDDIO 2.7V to 5.5V |
PDEC_3 | TtPL | TPCK low time | 2/fGCLK_PDEC | — | — | ns | |
PDEC_5 | TtPP | TPCK input period | 4/fGCLK_PDEC | — | — | ns | |
PDEC_7 | TCKEXTDLY | Delay from External TxCK Clock Edge to counter Increment | — | — | 4/fGCLK_PDEC | ns | |
PDEC_11 | TPDH | Position Decoder Input High Time | 2/fGCLK_PDEC | — | — | ns | |
PDEC_13 | TPDL | Position Decoder Input Low Time | 2/fGCLK_PDEC | — | — | ns | |
PDEC_15 | TPDIN | Position Decoder Input Period | 4/fGCLK_PDEC | — | — | ns | |
PDEC_21 | TPDFH | Filter Time to Recognize High, with Digital Filter | 4/fGCLK_PDEC | — | — | ns | |
PDEC_23 | TPDFL | Filter Time to Recognize Low, with Digital Filter | 4/fGCLK_PDEC | — | — | ns | |
PDEC_24 | PDECCLK | GCLK_PDEC | — | — | FCLK_29 | MHz |
VDDIO 2.7V to 5.5V. See parameter FCLK_29 in Maximum Clock Frequency table |