43.19 Sigma-Delta Analog-to-Digital Converter (SDADC) Electrical Specifications

Table 43-26. SDADC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
Device Supply
SDADC_1VDDANAADC Module Supply2.7V5.5VVVDD = VDDIO
Reference Inputs
SDADC_3VREF(2)ADC Reference Voltage 2.7VDDANAVVREF = VDDANA (REFCTRL.REFSEL = 0x3)
2.4VDDANAVVREF ≤ VDDANA

VREF = INTREF (REFCTRL.REFSEL = 0x0)

VREF = VREFB pin (REFCTRL.REFSEL = 0x1)

VREF = DAC output (REFCTRL.REFSEL = 0x2)

Analog Input Range
SDADC_7AFSFull-Scale Analog Input Signal Range (Single-Ended (1))GNDANA+VREFVVREF<VDDANA-0.3V, Gaincorr = 0x1
SDADC_8GNDANA+0.7 * VREFVVREF> = VDDANA-0.3V, Gaincorr = 0x1
SDADC_9Full-Scale Analog Input Signal Range (Differential)-VREF+VREFVVREF<VDDANA-0.3V, Gaincorr = 0x1
SDADC_10-0.7*VREF+0.7 * VREFVVREF> = VDDANA-0.3V, Gaincorr = 0x1
SDADC_11VcomInput Common mode voltageGNDANAAFS(max)VDifferential mode
Note:
  1. This mode corresponds to a differential mode where the selected AINx pin is externally grounded.
  2. SDADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. SDADC will function, but with degraded accuracy of approximately ~((0.06 * 2n) /VREF). Where "n" = #bits. SDADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users application noise or accuracy on VDDANA, GNDANA.
Table 43-27. SDADC Differential Mode Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
DIFFERENTIAL MODE ADC Accuracy
DSDADC_11ResResolution16bits
DSDADC_13ENOB (1,2,3,5)Effective Number of bits13bitsFTP(max), REFCTRL.REFSEL = 0x3 = VDDANA

VREF = VDDANA = 5.0V

DSDADC_19INL(3,5)Integral Nonlinearity-7.98.7LSb
DSDADC_25DNL(3,5)Differential Nonlinearity-1.03.3LSb
DSDADC_31GERR (3,5)Gain Error-771343LSb
DSDADC_37EOFF(3,5)Offset Error-229164LSb
DIFFERENTIAL MODE ADC Dynamic Performance
DSDADC_49SINAD (1,2,3,5)Signal to Noise and Distortion80.1dBFTP(max), REFCTRL.REFSEL = 0x3 = VDDANA

VREF = VDDANA = 5.0V

DSDADC_51SNR (1,2,3,6)Signal to Noise ratio85.0
DSDADC_53DR (1,2,3,6)Dynamic Range78.0
DSDADC_55THD (1,2,3,4,5)Total Harmonic Distortion-77.3
Note:
  1. Characterized with an analog input sine wave at 500Hz with OSR = 256.
  2. Sinewave peak amplitude = -3dB SDADC_ Full Scale amplitude input with 16bit resolution.
  3. Spec values collected under the following additional conditions:
    • All registers at reset default value otherwise not mentioned
  4. Value taken over 7 harmonics.
  5. Differential input mode, OSR = 256, SDADC Clock Period=166.7 ns (6 MHz), Chopper OFF (ANACTRL.ONCHOP = 0).
Table 43-28. SDADC Conversion Timing Requirements
AC CHARACTERISTICSStandard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
SDADC_ Clock Requirements
SDADC_57TADSDADC Clock Period166.71000ns
SDADC_58fGCLK_SDADCSDADC Module GCLK max input freq48MHz
SDADC_60OSROversampling ratio642561024TAD
SDADC Differential Mode Throughput Rates
SDADC_61FTPThroughput Rate (1) Free Running mode1/(TAD*4*OSR)kspsCTRLC.FREERUN = 1
Throughput Rate (1) Single Shot mode1/(TAD*4*(N+1)*OSR)CTRLC.FREERUN = 0, N = SKPCNT
Note:
  1. SDADC Throughput Rate FTP is divided by # of user active analog inputs in use on specific target SDADC module.
Table 43-29. SDADC Sample Timing Requirements
AC CHARACTERISTICSStandard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
SDADC_63SKPCNTskip count (1)215TADregister bits: CTRLB.SKPCNT[3:0]
SDADC_67TCNVConversion Time(1/FTP)/TADTAD
SDADC_69CSAMPLEInternal Sample Cap0.4250.50.575pF
SDADC_71RSAMPLE Internal input impedance1/(Csample*1/(4*TAD))kΩDifferential mode
1/(2 * Csample*1/(4*TAD))Single-Ended mode
SDADC_72RextInput anti-aliasing filter recommendation (2)1kΩ
Cext3.310nF
Note:
  1. Number of skip samples before retrieve the first valid sample. The first valid sample starts from the (SKPCNT+1)th sample onward.
  2. External anti-alias filter must be placed in front of each SDADC input to ensure high-frequency signals to not alias into measurement bandwidth. Use capacitors of X5R type for DC measurement, or capacitors of COG or NPO type for AC measurement.