43.16 Fractional Digital Phase Locked Loop (FDPLL96M)

Table 43-19. Fractional Digital Phase Locked Loop (FDPLL96M) Electrical specifications
AC CHARACTERISTICS Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
FDPLL_1 FDPLL_FIN FDPLL96M Input Frequency Range 32 — 2000 kHz —
FDPLL_3 FDPLL_FOUT FDPLL96M Output Clock Frequency 48 — 96 MHz —
FDPLL_5 FDPLL_Jitter FDPLL96M Period Jitter Pk-to-Pk (1,2) 1.4 — 3.6 % VDD = VDDIO = 5.0v,

fIN = 32.768 kHz from XOSC32K,

fOUT = 48 MHz

1 — 8.6 % VDD = VDDIO = 5.0v,

fIN = 32.768 kHz from XOSC32K,

fOUT = 96 MHz

FDPLL_7 1.4 — 3.9 % VDD = VDDIO = 5.0v,

fIN = 2 MHz from XOSC,

fOUT = 48 MHz

1 — 6.8 % VDD = VDDIO = 5.0v,

fIN = 2 MHz from XOSC,

fOUT = 96 MHz

FDPLL_11 FDPLL_SRT FDPLL96M Start-Up/Lock Time Time (1) — 1.1 — ms VDD = VDDIO = 5.0v,

fIN = 32.768 kHz from XOSC32K,

fOUT = 96 MHz

— 25 — µs VDD = VDDIO = 5.0v,

fIN = 2 MHz from XOSC,

fOUT = 96 MHz
Note:
  1. REFCLK for FDPLL96M is XOSC or XOSC32K.
  2. The provided jitter performance will be the best achieved on the device. Digital activity can increase jitter but is highly dependent on the application use model.
  3. DPLL jitter is sensitive to digital on-chip activity, which is application dependent.