43.5 CPU Standby Power

Table 43-8. CPU Standby Current Consumption Electrical Specifications
DC CHARACTERISTICS			Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	VDD = VDDIO	Typ.⁽¹⁾	Max.	Units	Conditions
SPWR_1	IDD_STANDBY⁽²⁾	CPU IDD in Standby mode XOSC32K running RTC running at 1 kHz	5.0V	15.1	585.5	µA	SRAM in Back Bias mode (PM.STDBYCFG.BBIASHS = 0x1), Low-Power regulator is used (PM.STDBYCFG.VREGSMODE = 0x2)
SPWR_3			3.3V	13.7	574.3	µA
SPWR_5			5.0V	60.9	650.3	µA	SRAM in Back Bias mode (PM.STDBYCFG.BBIASHS = 0x1), Main Regulator used (PM.STDBYCFG.VREGSMODE = 0x1)
SPWR_7			3.3V	57.2	645.1	µA
SPWR_9			5.0V	16	694.2	µA	SRAM in No Back Bias mode (PM.STDBYCFG.BBIASHS = 0x0), Low- Power regulator is used (PM.STDBYCFG.VREGSMODE = 0x2)
SPWR_11			3.3V	14.5	681.4	µA
SPWR_13			5.0V	61.9	765	µA	SRAM in No Back Bias mode (PM.STDBYCFG.BBIASHS = 0x0), Main Regulator used (PM.STDBYCFG.VREGSMODE = 0x1)
SPWR_15			3.3V	58.3	759.3	µA
SPWR_29		CPU IDD in Standby mode XOSC32K stopped RTC stopped	5.0V	13.6	580.1	µA	SRAM in Back Bias mode (PM.STDBYCFG.BBIASHS = 0x1), Low- Power regulator is used (PM.STDBYCFG.VREGSMODE = 0x2)
SPWR_31			3.3V	12.6	569.4	µA
SPWR_33			5.0V	59.3	642.5	µA	SRAM in Back Bias mode (PM.STDBYCFG.BBIASHS = 0x1), Main Regulator is used (PM.STDBYCFG.VREGSMODE = 0x1)
SPWR_35			3.3V	56.2	636.5	µA
SPWR_37			5.0V	14.4	690	µA	SRAM in No Back Bias mode (PM.STDBYCFG.BBIASHS = 0x0), Low Power regulator used (PM.STDBYCFG.VREGSMODE = 0x2)
SPWR_39			3.3V	13.5	677.6	µA
SPWR_41			5.0V	60.3	760	µA	SRAM in No Back Bias mode (PM.STDBYCFG.BBIASHS = 0x0), Main Regulator used (PM.STDBYCFG.VREGSMODE = 0x1)
SPWR_43			3.3V	57.2	754.3	µA
Note: Typical values at 25°C only. Conditions: System in standby mode No SleepWalking (except RTC when indicated) Peripheral modules are inactive (except RTC when indicated) All clocks stopped (CPU, AHB, APB, Main, GCLK, except RTC running at 1 KHz from XOSC32K when indicated) All clock generation sources disabled except XOSC32K running with external 32 kHz crystal when indicated All I/O pins configured as input pins pulled down or tied to GND WDT, CFD Clock Fail Detect disabled BODVDD disabled RESET = VDDIO.

Figure 43-3. Power Consumption Over Temperature in Standby Sleep Mode with RTC

Operating Conditions:

VDD = VDDIO = 5.0V