6.1.4.1.2 Using Harvard Architecture

When a system designer is more interested in optimal performance than flexibility, eSRAM_0 can be dedicated to the application (and ISRs), and eSRAM_1 can be dedicated to stack, heap, and buffering. This implies that the Cortex-M3 processor operates in a fully Harvard fashion, because eSRAM_0 can be accessed only by the combined code bus, and eSRAM_1 can be accessed by the system bus of M3 as well as the other (non-M3) masters.