6.1.4.1.1 Executing from eSRAM

The eSRAM remap is actually performed by aliasing the eSRAM blocks so they appear in the Cortex-M3 processor code space but are still accessible in the Cortex-M3 processor system space. Therefore, the system designer must allocate the eSRAM among clients in such a way that a portion of eSRAM allocated in one space (code space, for example) is left untouched in the other space (system space, for example).

The Cortex-M3 processor executes the application (including ISRs) from the code space, allowing optimal performance. However, the corresponding region in system space is grayed out. Conversely, the stack (and heap, if present) as well as buffering for non-M3 masters (such as peripheral DMA or Ethernet DMA) is allocated out of system space and so must be left grayed out in the code space.

This implementation is shown in the following figure.

This scheme allows flexibility to the system designer in choosing how much eSRAM is to be dedicated to each class of storage. For example, if the application, stack, and heap are small, this allows a large chunk of contiguous RAM to be allocated to buffering.