12.4.12 Line Status Register (LSR)

Table 12-19. LSR
Bit Number	Name	R/W	Reset Value	Description
7	FIER	R	0	This bit is set when there is at least one parity error, framing error, or break indication in FIFO. FIER is cleared when Cortex®-M3 processor reads the LSR, if there are no subsequent errors in the FIFO.
6	TEMT	R	1	Transmit empty (TEMT). This bit is set to 1 when both the transmitter FIFO and shift registers are empty.
5	THRE	R	1	Transmitter holding register empty (THRE). Indicates that the MMUART_x is ready to transmit a new data byte. THRE causes an interrupt to the Cortex-M3 processor when bit 1 (ETBEI) in the interrupt enable register is 1. This bit is set when the Tx FIFO is empty. It is cleared when at least one byte is written to the Tx FIFO.
4	BI	R	0	Break interrupt (BI). Indicates that the receive data is at 0 longer than a full word transmission time (start bit + data bits + parity + stop bits). BI is cleared when Cortex-M3 processor reads the line status register (Table 12-19). This error is revealed to the Cortex-M3 processor when it is associated character is at the top of the FIFO. When break occurs, only one zero character is loaded into FIFO.
3	FE	R	0	Framing error (FE). Indicates that the receive byte did not have a valid stop bit. FE is cleared when Cortex-M3 processor reads the Table 12-19. The MMUART_x tries to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this start bit twice, and then starts receiving the data. This error is revealed to Cortex-M3 processor when it is associated character is at the top of FIFO.
2	PE	R	0	Parity error (PE). Indicates that the receive byte had a parity error. PE is cleared when the Cortex-M3 processor reads the Table 12-19. This error is revealed to the Cortex-M3 processor when it is associated character is at the top of FIFO.
1	OE	R	0	Overrun error (OE). Indicates that the new byte was received before the Cortex-M3 processor reads the byte from the receive buffer, and that the earlier data byte was destroyed. OE is cleared when the Cortex-M3 processor reads the Table 12-19. If the data continues to fill the FIFO beyond the trigger level, an overrun error occurs once the FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the FIFO.
0	DR	R	0	Data ready (DR). Indicates when a data byte is received and stored in the receive buffer or the FIFO. DR is cleared to 0 when the Cortex-M3 processor reads the data from the receive buffer or the FIFO.

7

FIER

R

0

This bit is set when there is at least one parity error, framing error, or break indication in FIFO. FIER is cleared when Cortex®-M3 processor reads the LSR, if there are no subsequent errors in the FIFO.

6

TEMT

R

1

Transmit empty (TEMT). This bit is set to 1 when both the transmitter FIFO and shift registers are empty.

5

THRE

R

1

Transmitter holding register empty (THRE). Indicates that the MMUART_x is ready to transmit a new data byte. THRE causes an interrupt to the Cortex-M3 processor when bit 1 (ETBEI) in the interrupt enable register is 1. This bit is set when the Tx FIFO is empty. It is cleared when at least one byte is written to the Tx FIFO.

4

BI

R

0

Break interrupt (BI). Indicates that the receive data is at 0 longer than a full word transmission time (start bit + data bits + parity + stop bits). BI is cleared when Cortex-M3 processor reads the line status register (Table 12-19). This error is revealed to the Cortex-M3 processor when it is associated character is at the top of the FIFO. When break occurs, only one zero character is loaded into FIFO.

3

FE

R

0

Framing error (FE). Indicates that the receive byte did not have a valid stop bit. FE is cleared when Cortex-M3 processor reads the Table 12-19. The MMUART_x tries to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this start bit twice, and then starts receiving the data. This error is revealed to Cortex-M3 processor when it is associated character is at the top of FIFO.

2

PE

R

0

Parity error (PE). Indicates that the receive byte had a parity error. PE is cleared when the Cortex-M3 processor reads the Table 12-19. This error is revealed to the Cortex-M3 processor when it is associated character is at the top of FIFO.

1

OE

R

0

Overrun error (OE). Indicates that the new byte was received before the Cortex-M3 processor reads the byte from the receive buffer, and that the earlier data byte was destroyed. OE is cleared when the Cortex-M3 processor reads the Table 12-19. If the data continues to fill the FIFO beyond the trigger level, an overrun error occurs once the FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the FIFO.

0

DR

R

0

Data ready (DR). Indicates when a data byte is received and stored in the receive buffer or the FIFO. DR is cleared to 0 when the Cortex-M3 processor reads the data from the receive buffer or the FIFO.