12.4.17 Multi-Mode Control Register 2 (MM2)
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [7:4] | Reserved | R/W | 0 | The software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| 3 | ESWM | R/W | 0 | Enable single-wire, half-duplex mode. 0: Disabled (default) 1: Enabled |
| 2 | EAFC | R/W | 0 | Enable a flag clear (EAFC). When EAFM is enabled the Rx FIFO is disabled until another address flag with matching address is received. The bit gets cleared on write in multi-mode control registers 2. 0: Disabled (default) 1: Enabled |
| 1 | EAFM | R/W | 0 | Enable automatic 9-bit address flag mode (EAFM). It should be noted that for enabling this bit it requires, the LCR should be in an 8-bit and stick parity (SP) bit configured to 0. If EAFM bit is disabled, the Rx FIFO is enabled by receiving all the bytes. When EAFM bit is enabled, the Rx FIFO is disabled until an address flag with matching address is received. If an address match occurs and the Rx FIFO is enabled then it can be disabled, if either another address flag occurs or there is a mismatch or the EAFC bit is set. In either case, the Address flag compare will continue as long as the EAFM bit is set. 0: Disabled (default) 1: Enabled |
| 0 | EERR | R/W | 0 | When the EERR bit is set, the receiver forces an error signal transmit out, if an incoming parity error is detected. Error signal (ACK/NACK) is sent during stop time enable. The EERR only applies in an 8-bit data length, 2 stop bit configuration. Error signal occurs during the last 1.5 stop bits as per Figure 12-19. 0: Disabled (default) 1: Enabled |