21.5.71 Security Configuration Register for Masters 0, 1, and 2

Table 21-79. MM0_1_2_SECURITY
Bit Number	Name	Reset Value	Description
[31:10]	Reserved	0
9	MM0_1_2_MS6_ALLOWED_W	1	Write security bits for masters 0, 1, and 2 to slave 6 (MSS DDR bridge). If not set, masters 0, 1, and 2 will not have write access to slave 6.
8	MM0_1_2_MS6_ALLOWED_R	1	Read security bits for masters 0, 1, and 2 to slave 6 (MSS DDR bridge). If not set, masters 0, 1, and 2 will not have read access to slave 6.
7	MM0_1_2_MS3_ALLOWED_W	1	Write security bits for masters 0, 1, and 2 to slave 3 (eNVM1). If not set, masters 0, 1, and 2 will not have write access to slave 3.
6	MM0_1_2_MS3_ALLOWED_R	1	Read security bits for masters 0, 1 and 2 to slave 3 (eNVM1). If not set, masters 0, 1, and 2 will not have read access to slave 3.
5	MM0_1_2_MS2_ALLOWED_W	1	Write security bits for masters 0, 1, and 2 to slave 2 (eNVM0]) If not set, masters 0, 1, and 2 will not have write access to slave 2.
4	MM0_1_2_MS2_ALLOWED_R	1	Read security bits for masters 0, 1, and 2 to slave 2 (eNVM0). If not set, masters 0, 1, and 2 will not have read access to slave 2.
3	MM0_1_2_MS1_ALLOWED_W	1	Write security bits for masters 0, 1, and 2 to slave 1 (eSRAM1). If not set, masters 0, 1, and 2 will not have write access to slave 1.
2	MM0_1_2_MS1_ALLOWED_R	1	Read security bits for masters 0, 1, and 2 to slave 1 (eSRAM1). If not set, masters 0, 1, and 2 will not have read access to slave 1.
1	MM0_1_2_MS0_ALLOWED_W	1	Write security bits for masters 0, 1, and 2 to slave 0 (eSRAM0). If not set, masters 0, 1, and 2 will not have write access to slave 0.
0	MM0_1_2_MS0_ALLOWED_R	1	Read security bits for masters 0, 1, and 2 to slave 0 (eSRAM0). If not set, masters 0, 1, and 2 will not have read access to slave 0.

[31:10]

Reserved

0

9

MM0_1_2_MS6_ALLOWED_W

1

Write security bits for masters 0, 1, and 2 to slave 6 (MSS DDR bridge). If not set, masters 0, 1, and 2 will not have write access to slave 6.

8

MM0_1_2_MS6_ALLOWED_R

1

Read security bits for masters 0, 1, and 2 to slave 6 (MSS DDR bridge). If not set, masters 0, 1, and 2 will not have read access to slave 6.

7

MM0_1_2_MS3_ALLOWED_W

1

Write security bits for masters 0, 1, and 2 to slave 3 (eNVM1). If not set, masters 0, 1, and 2 will not have write access to slave 3.

6

MM0_1_2_MS3_ALLOWED_R

1

Read security bits for masters 0, 1 and 2 to slave 3 (eNVM1). If not set, masters 0, 1, and 2 will not have read access to slave 3.

5

MM0_1_2_MS2_ALLOWED_W

1

Write security bits for masters 0, 1, and 2 to slave 2 (eNVM0]) If not set, masters 0, 1, and 2 will not have write access to slave 2.

4

MM0_1_2_MS2_ALLOWED_R

1

Read security bits for masters 0, 1, and 2 to slave 2 (eNVM0). If not set, masters 0, 1, and 2 will not have read access to slave 2.

3

MM0_1_2_MS1_ALLOWED_W

1

Write security bits for masters 0, 1, and 2 to slave 1 (eSRAM1). If not set, masters 0, 1, and 2 will not have write access to slave 1.

2

MM0_1_2_MS1_ALLOWED_R

1

Read security bits for masters 0, 1, and 2 to slave 1 (eSRAM1). If not set, masters 0, 1, and 2 will not have read access to slave 1.

1

MM0_1_2_MS0_ALLOWED_W

1

Write security bits for masters 0, 1, and 2 to slave 0 (eSRAM0). If not set, masters 0, 1, and 2 will not have write access to slave 0.

0

MM0_1_2_MS0_ALLOWED_R

1

Read security bits for masters 0, 1, and 2 to slave 0 (eSRAM0). If not set, masters 0, 1, and 2 will not have read access to slave 0.