Table 21-5. ESRAM_MAX_LAT| Bit Number | Name | Reset Value | Description |
|---|
| [31:6] | Reserved | 0 | |
| [5:3] | SW_MAX_LAT_ESRAM1 | 0x1 | Defines the maximum number of cycles the
processor bus waits for eSRAM1 when it is being accessed by a master with a WRR
priority scheme. The latency values are as given in Table 21-6. |
| [2:0] | SW_MAX_LAT_ESRAM0 | 0x1 | Defines the maximum number of cycles the
processor bus waits for eSRAM0 when it is being accessed by a master with a WRR
priority scheme. It is configurable from 1 to 8 (8 by default). The latency
values are as given in Table 21-6. |
The following table lists eSRAM maximum latency values, where x is either 0 or 1.
Table 21-6. eSRAM Maximum Latency Values | SW_MAX_LAT_ESRAM<X> | Latency |
|---|
| 0 | 8 (default) |
| 1 | 1 |
| 2 | 2 |
| 3 | 3 |
| 4 | 4 |
| 5 | 5 |
| 6 | 6 |
| 7 | 7 |
