21.5.4 DDR Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:1] | Reserved | 0 | |
| 0 | SW_CC_DDRFWREMAP | 0 | Indicates that DDR_Space0 and DDR_Space1 are remapped to the lCODE/DCODE space of the Cortex-M3 processor. Both DDR spaces also remain visible in the SYSTEM space of the Cortex-M3 processor and remain visible at this location to all other non-Cortex-M3 processor masters. The bit definitions: 0: No DDR space remap is enabled. This means that eNVM is present at location 0x00000000. 1: DDR_Space0 and DDR_Space1 are remapped to location 0x00000000 of Cortex-M3 processor ICODE/DCODE space. |