21.5.73 Security Configuration Register for Masters 3, 6, 7, and 8

Table 21-81. MM3_6_7_8_SECURITY
Bit Number	Name	Reset Value	Description
[31:10]	Reserved	0
9	MM3_6_7_8_MS6_ALLOWED_W	1	Write security bits for masters 3, 6, 7, and 8 to slave 6 (MSS DDR bridge). If not set, masters 3, 6, 7, and 8 will not have write access to slave 6.
8	MM3_6_7_8_MS6_ALLOWED_R	1	Read security bits for masters 3, 6, 7, and 8 to slave 6 (MSS DDR bridge). If not set, masters 3, 6, 7, and 8 will not have read access to slave 6.
7	MM3_6_7_8_MS3_ALLOWED_W	1	Write security bits for masters 3, 6, 7, and 8 to slave 3 (eNVM1). If not set, masters 3, 6, 7, and 8 will not have write access to slave 3.
6	MM3_6_7_8_MS3_ALLOWED_R	1	Read security bits for masters 3, 6, 7, and 8 to slave 3 (eNVM1). If not set, masters 3, 6, 7, and 8 will not have read access to slave 3.
5	MM3_6_7_8_MS2_ALLOWED_W	1	Write security bits for masters 3, 6, 7, and 8 to slave 2 (eNVM0). If not set, masters 3, 6, 7, and 8 will not have write access to slave 2.
4	MM3_6_7_8_MS2_ALLOWED_R	1	Read security bits for masters 3, 6, 7, and 8 to slave 2 (eNVM0). If not set, masters 3, 6, 7, and 8 will not have read access to slave 2.
3	MM3_6_7_8_MS1_ALLOWED_W	1	Write security bits for masters 3, 6, 7, and 8 to slave 1 (eSRAM1). If not set, masters 3, 6, 7, and 8 will not have write access to slave 1.
2	MM3_6_7_8_MS1_ALLOWED_R	1	Read security bits for masters 3, 6, 7, and 8 to slave 1 (eSRAM1). If not set, masters 3, 6, 7, and 8 will not have read access to slave 1.
1	MM3_6_7_8_MS0_ALLOWED_W	1	Write security bits for masters 3, 6, 7, and 8 to slave 0 (eSRAM0). If not set, masters 3, 6, 7, and 8 will not have write access to slave 0.
0	MM3_6_7_8_MS0_ALLOWED_R	1	Read security bits for masters 3, 6, 7, and 8 to slave 0 (eSRAM0). If not set, masters 3, 6, 7, and 8 will not have read access to slave 0.

[31:10]

Reserved

0

9

MM3_6_7_8_MS6_ALLOWED_W

1

Write security bits for masters 3, 6, 7, and 8 to slave 6 (MSS DDR bridge). If not set, masters 3, 6, 7, and 8 will not have write access to slave 6.

8

MM3_6_7_8_MS6_ALLOWED_R

1

Read security bits for masters 3, 6, 7, and 8 to slave 6 (MSS DDR bridge). If not set, masters 3, 6, 7, and 8 will not have read access to slave 6.

7

MM3_6_7_8_MS3_ALLOWED_W

1

Write security bits for masters 3, 6, 7, and 8 to slave 3 (eNVM1). If not set, masters 3, 6, 7, and 8 will not have write access to slave 3.

6

MM3_6_7_8_MS3_ALLOWED_R

1

Read security bits for masters 3, 6, 7, and 8 to slave 3 (eNVM1). If not set, masters 3, 6, 7, and 8 will not have read access to slave 3.

5

MM3_6_7_8_MS2_ALLOWED_W

1

Write security bits for masters 3, 6, 7, and 8 to slave 2 (eNVM0). If not set, masters 3, 6, 7, and 8 will not have write access to slave 2.

4

MM3_6_7_8_MS2_ALLOWED_R

1

Read security bits for masters 3, 6, 7, and 8 to slave 2 (eNVM0). If not set, masters 3, 6, 7, and 8 will not have read access to slave 2.

3

MM3_6_7_8_MS1_ALLOWED_W

1

Write security bits for masters 3, 6, 7, and 8 to slave 1 (eSRAM1). If not set, masters 3, 6, 7, and 8 will not have write access to slave 1.

2

MM3_6_7_8_MS1_ALLOWED_R

1

Read security bits for masters 3, 6, 7, and 8 to slave 1 (eSRAM1). If not set, masters 3, 6, 7, and 8 will not have read access to slave 1.

1

MM3_6_7_8_MS0_ALLOWED_W

1

Write security bits for masters 3, 6, 7, and 8 to slave 0 (eSRAM0). If not set, masters 3, 6, 7, and 8 will not have write access to slave 0.

0

MM3_6_7_8_MS0_ALLOWED_R

1

Read security bits for masters 3, 6, 7, and 8 to slave 0 (eSRAM0). If not set, masters 3, 6, 7, and 8 will not have read access to slave 0.