21.5.2 eSRAM Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:2] | Reserved | 0 | |
| 1 | SW_CC_ESRAM1FWREMAP | 0 | Defines the locations of eSRAM_0 and eSRAM_1 if eSRAM remap is enabled (if SW_CC_ESRAMFWREMAP is asserted). If SW_CC_ESRAMFWREMAP is 0, this bit has no meaning. If SW_CC_ESRAMFWREMAP is 1, this bit has the following definition: 0: eSRAM_0 is located at address 0x00000000 in the ICODE/DCODE space of Cortex-M3 processor and eSRAM_1 is located just above eSRAM_0 (adjacent to it). 1: eSRAM_1 is located at address 0x00000000 in ICODE/DCODE space of Cortex-M3 processor and eSRAM_0 is located just above eSRAM_1 (adjacent to it). |
| 0 | SW_CC_ESRAMFWREMAP | 0 | Indicates that eSRAM_0 and eSRAM_1 are remapped to lCODE/DCODE space of the Cortex-M3 processor. If this bit is 1 and SW_CC_ESRAM1FWREMAP is 0, then eSRAM_0 is at location 0x00000000 and eSRAM_1 is always remapped to be just above eSRAM_0 (the two eSRAMs are adjacent in ICODE/DCODE space). Both eSRAMs also remain visible in SYSTEM space of the Cortex-M3 processor and remain visible at this location to all other (non-Cortex-M3 processor) masters. The bit definitions: 0: No eSRAM remap is enabled. This means that eNVM (or MDDR) is present at location 0x00000000. 1: eSRAM_0 and eSRAM_1 are remapped to location 0x00000000 of Cortex-M3 processor ICODE/DCODE space. |