21.5.6 eNVM Remap Base Address Control Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:19] | Reserved | 0 | |
| [18:1] | SW_ENVMREMAPBASE | 0 | Offset within eNVM address space of the base address of the segment in eNVM, which is to be remapped to location 0x00000000. If an eNVM protected region is defined to be read-accessible by the Cortex-M3, then it is read-accessible by Cortex-M3 at both physical and re-mapped addresses. However, if a protected region is defined as writeable by Cortex-M3, then it is writeable via the physical address, but not via the re-mapped address. Bit 0 of this register is defined as SW_ENVMREMAPENABLE. Bit 0 must be set to get the remapping done with new addresses filled in this register. |
| 0 | SW_ENVMREMAPENABLE | 0 | 0: eNVM remap not enabled. Bottom of eNVM is mapped to address 0x00000000. 1: eNVM remap enabled. eNVM visible at 0x00000000 is a remapped segment of the eNVM. |
Bits [18:N] of this bus indicate the base address of the remapped segment. The value of N depends on the eNVM remap section size, so that the base address is aligned according to an even multiple of the segment size. The power of 2 size specified by SW_ENVMREMAPSIZE[4:0] (Table 21-9) defines how many bits of the base address are used. For example, if the SW_ENVMREMAPSIZE[4:0] is 01111, this corresponds to a segment size of 64 KB. 64 KB is 2 to the power of 16. Therefore the value of N in this case, is 16. So the base address of the region, in this case, is specified by SW_ENVMREMAPSIZE[18:16].
This register should only be written by Cortex-M3 processor firmware using 32-bit accesses. The behavior of the system is undefined if other size accesses are used.