9.2.10 NVM ECC Fault Injection Pointer Register

Table 9-11. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	NVMECCFPTR
Offset:	0x3024


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	FLT2PTR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FLT1PTR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:8 – FLT2PTR[7:0] ECC Fault Injection Bit Pointer 2

Value	Description
11111111-10001001	No Fault injection occurs
10001000	Fault injection (bit inversion) occurs on bit 136 of ECC bit order
...
00000001	Fault injection (bit inversion) occurs on bit 1 of ECC bit order
00000000	Fault injection (bit inversion) occurs on bit 0 of ECC bit order

Bits 7:0 – FLT1PTR[7:0] ECC Fault Injection Bit Pointer 1

Value	Description
11111111-10001001	No Fault injection occurs
10001000	Fault injection (bit inversion) occurs on bit 136 of ECC bit order
...
00000001	Fault injection (bit inversion) occurs on bit 1 of ECC bit order
00000000	Fault injection (bit inversion) occurs on bit 0 of ECC bit order

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.