9.2.19 NVM CRC Control Register

Table 9-20. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	NVMCRCCON
Offset:	0x3048


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	DELAY[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CRCEN	START					CRCIDL[1:0]
Access	R/W	R/W					R/W	R/W
Reset	0	0					0	0


Bit	7	6	5	4	3	2	1	0
							CRCEC[1:0]
Access							R/HS/HC	R/HS/HC
Reset							0	0

Bits 23:16 – DELAY[7:0] Delay Between CRC Accesses bits

Delay count in system clock cycles between CRC accesses

Bit 15 – CRCEN Enable CRC Function bit

Value	Description
`1`	CRC function enabled
`0`	CRC function disabled

Bit 14 – START Start CRC Calculation bit

Value	Description
`1`	Start CRC calculation (CRC in progress)
`0`	CRC calculation complete (CRC function idle)

Bits 9:8 – CRCIDL[1:0] Idle Operation Control bits

Value	Description
11	Reserved
10	CRC operates in Idle mode and is stopped in CPU Run mode
01	CRC operates in CPU Run mode and is stopped in Idle mode
00	CRC operates in CPU Run mode and Idle mode

Bits 1:0 – CRCEC[1:0] CRC Error Code bits

Value	Description
11	Invalid address (start address greater than end address)
10	Flash ECC DED error
01	Security access control violation
00	No error

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