9.2.9 NVM ECC Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | NVMECCSTAT |
| Offset: | 0x3020 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ESEL | FLEC[1:0] | ||||||||
| Access | R/W | R | R | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SECO | SEC | DEDO | DED | ||||||
| Access | R/C/HS | R/C/HS | R/C/HS | R/C/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 12 – ESEL Error Reporting Select bit
| Value | Description |
|---|---|
1 | Select SEC information for ECCEADDR, ECCEDATAx, ECCVAL, ECCSYN registers |
0 | Select DED information for ECCEADDR, ECCEDATAx, ECCVAL, ECCSYN registers |
Bits 9:8 – FLEC[1:0] Fuse Load Error Code
| Value | Description |
|---|---|
| 11 | One or more DED errors; one or more default fuse values were used |
| 10 | One or more DED errors; no default fuse values were used |
| 01 | One or more SEC errors; no DED errors |
| 00 | No ECC bit errors |
Bit 5 – SECO SEC Event Overflow bit
| Value | Description |
|---|---|
1 | SEC error not captured due to overflow |
0 | No SEC error overflow reported |
Bit 4 – SEC SEC Event Reported bit
| Value | Description |
|---|---|
1 | Single-bit error reported |
0 | Single-bit error not reported |
Bit 1 – DEDO DED Event Overflow bit
| Value | Description |
|---|---|
1 | DED error not captured due to overflow |
0 | No DED error overflow reported |
Bit 0 – DED DED Event Reported bit
| Value | Description |
|---|---|
1 | Double-bit error reported |
0 | Double-bit error not reported |