This register is readable only when NVMCON.WREN = 0.
This register is not readable when NVMCON.WREN = 1. An
attempted read will return (by convention) all ‘1’s.
This register is cleared after a Flash write operation completes (when
NVMCON.WR returns to ‘0’).
This register is also mapped
into user address space as SLVDATAL.
Table 9-7. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
NVMDATA3
Offset:
0x3014
Reset:
0
Property:
R/W
Bit
31
30
29
28
27
26
25
24
DATA3[127:120]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DATA3[119:112]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DATA3[111:104]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA3[103:96]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – DATA3[127:96]
NVM Write Data Register(1,2,3,4,5)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
