This address must be aligned to a RAM word address (word-aligned).
Table 9-8. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
NVMSRCADR
Offset:
0x3018
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
SRCADR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
SRCADR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SRCADR[7:2]
Access
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
Bits 23:16 – SRCADR[23:16] RAM Base Address
register for row programming
The address is always on 32-bit
word boundaries.
Bits 15:8 – SRCADR[15:8] RAM Base Address
register for row programming
The address is always on 32-bit
word boundaries.
Bits 7:2 – SRCADR[7:2] RAM Base Address register for row
programming
The address is always
on 32-bit word boundaries.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
