| Product Identification System | Updated example |
| Microchip Recommended Power Management Solutions | Updated Figure 1-4 and Figure 1-5 |
| Memory Mapping | Figure 1-6: corrected SYSCWP offset |
| Peripheral Identifiers | Table 1-6: restored GMAC (ID 67) row; updated PMECC (ID 48) row |
| Memories | Updated Clocks |
| Static Memory Controller (SMC) |
Updated Figure 3-12
SMC_OCMS: corrected field name to CSxSE
|
| Programmable Multibit ECC Error Location Controller (PMERRLOC) |
PMERRLOC_SIGMA0:
renamed field from SIGMA0 to SIGMA
PMERRLOC_SIGMAx:
renamed field from SIGMAx to SIGMA
|
| Real-Time Clock (RTC) |
Updated UTC Mode
Updated RTC_TSTRx, RTC_TSDRx, RTC_TSSRx register descriptions
RTC_MR:
updated UTC and HRMODE descriptions
RTC_TIMALR (DEFAULT_MODE):
updated AMPM description
|
| Debug Unit (DBGU) |
Updated Chip Identifier and DBGU_CIDR
|
| Special Function Registers (SFR) |
SFR_TSU_CFG:
updated WIDTH description
|
| Power Management Controller (PMC) |
Updated Spread Spectrum
|
| Parallel Input/Output Controller (PIO) |
PIO_ABCDSR1 and PIO_ABCDSR2 renamed PIO_ABCDSR0 and PIO_ABCDSR1
PIO_DRIVER1 renamed PIO_DRIVER
|
| Analog-to-Digital Controller (ADC) |
Added ADC Input Sampling Capacitor Charging Time (Tracking Time), Maximum Sampling Frequency
Analog-to-Digital Conversion:
updated tracking time information
ADC_MR:
updated TRACKTIM description
ADC_ACR:
corrected reset value; updated IBCTL description
ADC_EMR:
updated TRACKX4 description
|
| LCD Controller (LCDC) |
Split the LCDC_LCDCFG5 register into LCDC_LCDCFG5 (DEFAULT_MODE) and LCDC_LCDCFG5 (DPI-COMPLIANT_MODE)
|
| 2D Graphics Engine (GFX2D) |
BLEND_WD5:
updated SPRE and DPRE descriptions
|
| Display Serial Interface (DSI) |
High-Speed Frequency Range Control Operation:
updated Table 6-105
D-PHY PLL Control Operation:
updated Table 6-106
|
| Camera Serial Interface (CSI) |
Added Data ID Monitors
Added the following registers: Updated CSI_INT_ST_MAIN
CSI_SCRAMBLING_SEED3:
corrected reset value
|
| Image Sensor Controller (ISC) | Embedded Characteristics: updated Parallel Interface characteristic |
| Inter-IC Sound Multi-Channel Controller (I2SMCC) |
Updated Monitors and Reports
DMA Controller Operation:
added Table 7-6 and Table 7-7
I2SMCC_MRB:
updated DMACHUNK description
I2SMCC_IERA,
I2SMCC_IDRA,
I2SMCC_IMRA,
I2SMCC_ISRA:
removed bits with indexes greater than 0
|
| Advanced Encryption Standard (AES) |
Updated Start Modes, Encrypted Tweak Generation,
Data Processing
XEX-based Tweaked-codebook Mode (XTS):
updated auto-padding information
|
| Secure Hash Algorithm (SHA) |
Updated Description, SHA Algorithm,
Protocol Layers Improved Performances
SHA_WPMR:
updated ACTION description
SHA_CR:
updated SWRST description
SHA_MR:
corrected ALGO description
SHA_ISR:
corrected URAT description
|
| Triple Data Encryption Standard (TDES) |
Updated Security and Safety Analysis and Reports
TDES_MR:
modified PKRS description
|
| Ethernet MAC (GMAC) |
Updated 1588 Timestamp Unit
Table 9-2: updated field 12:0
GMAC_MAN:
updated OP description
GMAC_TSCTL:
corrected field name from TXSQ0 to TXSQ
|
| Flexible Serial Communication Controller (FLEXCOM) |
Modified content regarding multiple data reading in SPI Multiple Data Access, FLEX_SPI_RDR (FIFO_MULTI_DATA_8), FLEX_SPI_RDR (FIFO_MULTI_DATA_16)
Updated Table 9-18
FLEX_SPI_RDR (FIFO_MULTI_DATA_8),
FLEX_SPI_RDR (FIFO_MULTI_DATA_16),
FLEX_SPI_TDR (FIFO_MULTI_DATA):
“FIFO” removed from register name (but kept in register acronym)
|
| Quad Serial Peripheral Interface (QSPI) |
Updated Scrambling/Unscrambling Function, Data Strobe Delay Management
|
| Secure Digital MultiMedia Card Controller (SDMMC) |
Split the SDMMC SDMA System Address/Argument 2 Register into SDMMC_SSAR (DEFAULT_MODE) and
SDMMC_SSAR (CMD23)
|
| USB Device High Speed Port (UDPHS) |
Updated Power Management
Added Detach Procedure (Software Disconnect)
Transfer Without DMA:
updated “Important” note
Register Summary:
corrected format of registers suffixed with “(DEFAULT_MODE)”
UDPHS_CTRL:
updated DETACH description
UDPHS_TST:
updated SPEED_CFG description
|
| USB Host High Speed Port (UHPHS) |
Updated Figure 10-22
|
| Electrical Characteristics |
12-bit ADC Characteristics:
added table footnote (1)
Updated Table 11-50, Table 11-67, Flexible Serial Communication Controller
(FLEXCOM) - USART
|
