10.11.5 PLL Output Divider Register
Note:
- The POST1DIVx and POST2DIVx divider values must not be changed while the PLL is operating.
- The default values for POST1DIVx and POST2DIVx are 4 and 1, respectively, yielding a 150 MHz system source clock.
| Name: | PLLDIV |
| Offset: | 0xF8A |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VCODIV[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| POST1DIV[2:0] | POST2DIV[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 9:8 – VCODIV[1:0] PLL VCO Output Divider Select bits
| Value | Description |
|---|---|
| 11 | FVCO |
| 10 | FVCO/2 |
| 01 | FVCO/3 |
| 00 | FVCO/4 |
Bits 6:4 – POST1DIV[2:0] PLL Output Divider #1 Ratio bits(1,2)
POST1DIV[2:0] can have a valid value, from 1 to 7 (POST1DIVx value should be greater than or equal to the POST2DIVx value). The POST1DIVx divider is designed to operate at higher clock rates than the POST2DIVx divider.
Bits 2:0 – POST2DIV[2:0] PLL Output Divider #2 Ratio bits(1,2)
POST2DIV[2:0] can have a valid value, from 1 to 7 (POST1DIVx value should be greater than or equal to the POST2DIVx value). The POST1DIVx divider is designed to operate at higher clock rates than the POST2DIVx divider.