10.11.6 Auxiliary Clock Control Register
Note:
- Even with the APLLEN bit set, another peripheral must generate a clock request before the APLL will start.
Legend: r = Reserved bit
| Name: | ACLKCON1 |
| Offset: | 0xF8E |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| APLLEN | APLLCK | FRCSEL | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved[1:0] | APLLPRE[3:0] | ||||||||
| Access | r | r | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 15 – APLLEN Auxiliary PLL Enable/Bypass Select bit(1)
| Value | Description |
|---|---|
1 |
AFPLLO is connected to APLL post-divider output (bypass is disabled) |
0 |
AFPLLO is connected to APLL input clock (bypass is enabled) |
Bit 14 – APLLCK APLL Phase-Locked State Status bit
| Value | Description |
|---|---|
1 |
Auxiliary PLL is in lock |
0 |
Auxiliary PLL is not in lock |
Bit 8 – FRCSEL FRC Clock Source Select bit
Bits 5:4 – Reserved[1:0]
Read as ‘0’
Bits 3:0 – APLLPRE[3:0] Auxiliary PLL Phase Detector Input Divider bits
| Value | Description |
|---|---|
1111 |
Reserved |
| . . . | |
1001 |
Reserved |
1000 |
Input divided by 8 |
0111 |
Input divided by 7 |
0110 |
Input divided by 6 |
0101 |
Input divided by 5 |
0100 |
Input divided by 4 |
0011 |
Input divided by 3 |
0010 |
Input divided by 2 |
0001 |
Input divided by 1 (power-on default selection) |
0000 |
Reserved |