10.11.11 Reference Clock Control High Register
| Name: | REFOCONH |
| Offset: | 0xFBA |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RODIV[14:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RODIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 14:0 – RODIV[14:0] Reference Clock Integer Divider Select bits
Divider for the selected input clock source is two times the selected value.
| Value | Description |
|---|---|
111 1111 1111
1111 |
Base clock value divided by 65,534 (2 * 7FFFh) |
111 1111
1111 1110 |
Base clock value divided by 65,532 (2 * 7FFEh) |
111 1111
1111 1101 |
Base clock value divided by 65,530 (2 * 7FFDh) |
| . . . | |
000 0000
0000 0010 |
Base clock value divided by 4 (2 * 2) |
000 0000
0000 0001 |
Base clock value divided by 2 (2 * 1) |
000 0000
0000 0000 |
Base clock value |