10.11.10 Reference Clock Control Low Register

Legend: HC = Hardware Clearable bit; HSC = Hardware Settable/Clearable bit

Name:	REFOCONL
Offset:	0xFB8


Bit	15	14	13	12	11	10	9	8
	ROEN		ROSIDL	ROOUT	ROSLP		ROSWEN	ROACTIV
Access	R/W		R/W	R/W	R/W		R/W/HC	R/HSC
Reset	0		0	0	0		0	0


Bit	7	6	5	4	3	2	1	0
					ROSEL[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bit 15 – ROEN Reference Clock Enable bit

Value	Description
`1`	Reference Oscillator is enabled on the REFCLKO pin
`0`	Reference Oscillator is disabled

Bit 13 – ROSIDL Reference Clock Stop in Idle bit

Value	Description
`1`	Reference Oscillator is disabled in Idle mode
`0`	Reference Oscillator continues to run in Idle mode

Bit 12 – ROOUT Reference Clock Output Enable bit

Value	Description
`1`	Reference clock external output is enabled and available on the REFCLKO pin
`0`	Reference clock external output is disabled

Bit 11 – ROSLP Reference Clock Stop in Sleep bit

Value	Description
`1`	Reference Oscillator continues to run in Sleep modes
`0`	Reference Oscillator is disabled in Sleep modes

Bit 9 – ROSWEN Reference Clock Output Enable bit

Value	Description
`1`	Clock divider change (requested by changes to RODIVx) is requested or is in progress (set in software, cleared by hardware upon completion)
`0`	Clock divider change has completed or is not pending

Bit 8 – ROACTIV Reference Clock Status bit

Value	Description
`1`	Reference clock is active; do not change clock source
`0`	Reference clock is stopped; clock source and configuration may be safely changed

Bits 3:0 – ROSEL[3:0] Reference Clock Source Select bits

Value	Description
`1111`	Reserved
. . .	Reserved
`1000`	Reserved
`0111`	REFI pin
`0110`	F_VCO/4
`0101`	BFRC
`0100`	LPRC
`0011`	FRC
`0010`	Primary Oscillator
`0001`	Peripheral clock (F_P)
`0000`	System clock (F_OSC)

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