10.11.8 APLL Output Divider Register
Note:
- The APOST1DIVx and APOST2DIVx values must not be changed while the PLL is operating.
- The default values for APOST1DIVx and APOST2DIVx are 4 and 1, respectively, yielding a 150 MHz system source clock.
| Name: | APLLDIV1 |
| Offset: | 0xF92 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AVCODIV[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| APOST1DIV[2:0] | APOST2DIV[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 1 | |||
Bits 9:8 – AVCODIV[1:0] APLL VCO Output Divider Select bits
| Value | Description |
|---|---|
11 |
AFVCO |
10 |
AFVCO/2 |
01 |
AFVCO/3 |
00 |
AFVCO/4 |
Bits 6:4 – APOST1DIV[2:0] APLL Output Divider #1 Ratio bits(1,2)
APOST1DIV[2:0] can have a valid value, from 1 to 7 (the APOST1DIVx value should be greater than or equal to the APOST2DIVx value). The APOST1DIVx divider is designed to operate at higher clock rates than the APOST2DIVx divider.
Bits 2:0 – APOST2DIV[2:0] APLL Output Divider #2 Ratio bits(1,2)
APOST2DIV[2:0] can have a valid value, from 1 to 7 (the APOST2DIVx value should be less than or equal to the APOST1DIVx value). The APOST1DIVx divider is designed to operate at higher clock rates than the APOST2DIVx divider.